As the application of the consuming electronic products being used extensively, more and more functions can be worked on the same chip. Different function blocks may need different supply voltage. Considering of power consumption, circuit operated at low voltage and low current can achieve power reduction. Due to the energy crisis nowadays, plenty of products begin to focus on the green power. The main advantage of green power is saving power, which will not affect the efficiency. In addition, while the CMOS technology process evolves all the time, the stability of the operation voltage needs to be reduced by the advancement. Thus, the power management in a 3D graphic chip application is going to be introduced in this thesis. Utilizing the linear regulator to reduce the DC to 1.2, 1.1, 1.0, 0.9 and 0.8 V from 3.3V, and support a stable voltage for core circuits and I/O circuits. With the emphasis on the circuit efficiency is affected by power management, the level shifter to embed normal useful digital logic is also investigated. When using in the logic gates, it can reduce power consumption simultaneously. Therefore, it is important to adopt power IC in the future.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0729109-232541 |
| Date | 29 July 2009 |
| Creators | Chen, Sheng-quane |
| Contributors | Chia-Hsiung Kao, Ko-Chi Kuo, Shiann-Rong Kuang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729109-232541 |
| Rights | not_available, Copyright information available at source archive |
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