In this thesis, An automatic optimization logic synthesizer in pass-transistor-based is developed for logic mapping of the combinational circuits. The format of inputs is Boolean functions with expression of sum of product and we can input several functions for hardware sharing at the same time. Depending the difference of circuits, we use the RC delay model to do optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. It only needs little executing time for searching the best result and we can quickly gate it.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0807100-134215 |
| Date | 07 August 2000 |
| Creators | Hsu, Chih-Cheng |
| Contributors | Shen-Fu Hsiao, Chua-Chin Wang, Chieh-Hsing Wu |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807100-134215 |
| Rights | unrestricted, Copyright information available at source archive |
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