As the complexity of SoC increases rapidly, embedded memory becomes one of the critical components in current SoC design. In this thesis, we develop a memory generator so that users can easily integrate proper embedded memory circuits into SoC chips. The generator is based on a low-power multi-voltage-source memory architecture that partitions the complete memory into two parts to avoid unnecessary operations. In addition, we also address the modification of the memory architectures in order to provide more efficient data accessing in multimedia applications such as DCT, JPEG-2000 and 3D graphics. The developed memory generator can produce all the necessary files required in the traditional cell-based design flow, including behavior model, Synopsys library, LEF file, Spice netlists and layouts, so that the designers can easily utilize the generated memory units in their ASIC designs.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0815106-105854 |
| Date | 15 August 2006 |
| Creators | Chen, Yu-Chi |
| Contributors | Chung-Ho Chen, Ko-Chi Kuo, Ing-Jer Huang, Shen-Fu Hsiao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0815106-105854 |
| Rights | campus_withheld, Copyright information available at source archive |
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