This paper proposed a scalable chip multiprocessor architecture, which is called Hyper-scalar combined with the concept of superscalar and multithreaded architecture; hence, this architecture can enhance single-threaded performance by using core group and also supports multithreaded applications. System programmer can dynamically allocate the core groups to accelerate a single thread by extended system instructions. In order to solve the data dependence between all issued instructions the virtual shared register file is proposed.
This mechanism allows the data in local register files to be accessed from other cores through the data switching path hardware and the instructions are executed only when the operands are available. The instructions within a single-threaded application can be dispatched to variable cores without re-compilation. This execution paradigm accelerates the single-threaded performance more flexibly.
In the case of simulation and experimental framework, the ESL Model written in SystemC, a modeling language based on C++ is to provide hardware-oriented simulation platform and the MediaBench suite is selected for the experiments. On average, the Hyper-scalar architecture can accelerate single-threaded performance by 30% to 110% using 2 ~ 8 cores.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0820107-003959 |
| Date | 20 August 2007 |
| Creators | Chen, Po-kai |
| Contributors | Chung-Ping Chung, Tsung Lee, Jih-ching Chiu, Shen-Fu Hsiao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820107-003959 |
| Rights | unrestricted, Copyright information available at source archive |
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