In this thesis, compared to the conventional pseudo gate all around SOI MOSFET, a similar device is successfully implemented already. This three dimension structure illustrate a pseudo gate all around SOI MOSFET which contains at least four advantages as listed in the following:
(1). Using nearly pseudo gate all around to substitute a conventional single gate structure; in this new design, except the poly-silicon gate formed above the silicon film layer, we further implement a tetragonal-like gate in the beneath, front and back sides of the aforementioned silicon film layer. Such tetragonal-like gate can reach some goals obviously, like better gate controllability and stronger current drive.
(2). The simulation of pseudo gate all around will be compared to a conventional pseudo gate all around by many different electric features to verify that this type of structure should have possibly higher manufacture yield and reliable characteristic.
(3). We can separate the gate into the above gate and the beneath gate to form a four terminals device. By applying different touching electrodes to the two gates, we can bring the gate controllability up, and strengthen the current drive, and suppress some negative effects of the device.
(4). Pseudo gate all around device will be simpler compared to a conventional pseudo gate all around device in the manufacture effort, so it is easier for devices miniaturization in the future, and it can also improve some shortages, like hard-etching and hole-fulfillment, the technical issues in the conventional pseudo gate all arounds device, thus the devices manufacture yield will be brought up greatly, even a conventional pseudo gate all arounds device is applied to thin-film transistor made way, it still needs more one mask for holes plight compared to a pseudo gate all arounds device, it will reflect to the investment.
The simulation tool ISE TCAD is being courtesy of the simulation for pseudo gate all around device structure to verify the feasibility of manufacture and process. And TCAD Dessis is applied to simulate I-V characteristic and other electric analysis. Based on the different curves simulated, we reach the conclusion: put this pseudo gate all around device on the comparison with a conventional pseudo gate all around device, in the following items, threshold voltage, sub-threshold factor are drawn. Incredibly, our design has a flattered input curve and less leakage Ioff, respectively. In the output curve, our work has harvester saturated current and finally, by different structure of simulated result to verify the active region depth may eliminate ¡§kink effect¡¨ under 50nm.
Hence, pseudo gate all around SOI MOSFET will be more potentially applied to ULSI (ultra large schematic integrated circuit) in the future, compared to other previous SOI devices.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0824107-155132 |
| Date | 24 August 2007 |
| Creators | Chen, Ho-Ting |
| Contributors | Jyi-Tsong Lin, Ming-Kwei Lee, Yao-Tsung Tsai, Ting-Chang Chang, James-Bang Kuo |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824107-155132 |
| Rights | not_available, Copyright information available at source archive |
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