In recent years, the Ultra-wideband (UWB) has become one of the most important
transmission technologies in the wireless personal area networks (WPAN). In this thesis,
we will focus on the multi-band orthogonal frequency division multiplexing (MB-OFDM)
based UWB and investigate the hardware implementation of the Fast Fourier Transform
(FFT) processor required by the baseband receiver. Due to the requirement of high data
rate transmission, a pipeline structure is adopted for parallel processing at a lower clock
rate. The hardware implementation is first verified and simulated by using the Verilog
hardware description language (HDL). Then, the proposed design is realized by the
Taiwan Semiconductor Manufacturing Company (TSMC) 0.13 £gm single-poly
eight-metal CMOS process.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0827107-092813 |
| Date | 27 August 2007 |
| Creators | Tsou, Chih-lung |
| Contributors | Chih-Peng Li, Ding-Bing Lin, Yuh-Ren Tsai, Chin-Liang Wang, Jhy-Horng Wen |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0827107-092813 |
| Rights | not_available, Copyright information available at source archive |
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