When the conventional FDTD method is applied to the high-frequency planar circuits, the time step must be very small due to the CFL stability criterion since the structural details of the circuits are usually very small. These results in a prohibitively high computation time since the simulation takes a long time to stabilize. This thesis will focus on implementing an ADI-FDTD algorithm suitable for the analysis and simulation of large-scale high-frequency planar circuits. Realization of the lumped elements befitting the ADI-FDTD algorithm will be developed. Furthermore, active devices will then be incorporated into the algorithm once the models for lumped elements are built up.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0903107-170011 |
| Date | 03 September 2007 |
| Creators | Lin, Zheng-Hong |
| Contributors | Ming-Cheng Liang, Tzyy-Sheng Horng, Chih-Wen Kuo, Ken-Huang Lin |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0903107-170011 |
| Rights | not_available, Copyright information available at source archive |
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