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An Implementation of Low-Power Turbo Decoder for 3GPP

Because of the simple architecture and excellent error correcting capability, Turbo code has been adopted in many wireless communication standards, including the third generation wireless communication systems, 3GPP and 3GPP2. However, low power turbo decoder design would become the most important issue in mobile communication systems because of the limited battery life.
In the thesis, we use the cyclic redundancy check (CRC) as the stopping criterion in the implementation of turbo decoder design to reduce the unnecessary power consumption. We use the MATLAB simulation and FPGA simulation to verify our design.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0907104-173755
Date07 September 2004
CreatorsCheng, Chin-ren
ContributorsChih-Peng Li, Yun-Nan Chang, Yung-Fang Chen
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907104-173755
Rightsnot_available, Copyright information available at source archive

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