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FPGA-based co-processor for singular value array reconciliation tomography

Thesis (M.S.)--Worcester Polytechnic Institute. / Keywords: hardware accelerator; SVD; digital signal processing; FPGA. Includes bibliographical references (leaves 115-117).

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/426032331
Date January 2007
CreatorsCoyne, Jack W.
PublisherWorcester, Mass. : Worcester Polytechnic Institute,
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish
SourceLink to electronic thesis

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