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Sparse hierarchical model order reduction for high speed interconnects

Thesis (M.Eng.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2009/06/17). Includes bibliographical references.

Identiferoai:union.ndltd.org:OCLC/oai:xtcat.oclc.org:OCLCNo/429187991
Date January 2009
CreatorsQiao, Hao.
Source SetsOCLC
LanguageEnglish
Detected LanguageEnglish

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