While the performance gap between microprocessors and main memory is
ever increasing each year, cache memory has been a bridge to alleviate this
discrepancy. In this thesis proposal, we introduce three techniques to tolerate this
processor and memory speed imbalance. First, we propose the bloom filter scheme
to identify which load operant could cause cache miss. Second, we explore a new
fault-tolerant microarchitecture to detect transient error occurs. Third, we proposed
a novel hardware-only mechanism to solve pointer-chasing problem in Link-list
Data Structure application. The simulation shows that the bloom filter may filter
out 99% of cache miss. The new fault-tolerant microarchitecture reduce the penalty
caused by detecting instruction error about 1.8-13%. The hardware-only data
prefetch mechanism accurate predict over 80% of irregular address pattern and
improve the performance by 7%. / Graduation date: 2003
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/30423 |
| Date | 31 October 2002 |
| Creators | Lai, Shih-Chang |
| Contributors | Lu, Shih-Lien |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
Page generated in 0.002 seconds