The purpose of this research is to develop an approach to minimize
makespan for assigning boards to production lines. Because of sequence-dependent
setup issue, board assignment and component allocation have to be performed
concurrently. An integrated methodology is proposed to obtain a solution of the
two problems. The methodology consists of seven phases: PCB grouping, family
decomposition, subfamily sequencing, Keep Tool Needed Soonest (KTNS),
component setup determination, component allocation, and board assignment.
PCB grouping based on component similarity between boards is used to
reduce the problem size. Family decomposition is used when total number of feeder
slots required by a family exceeds feeder capacity. Subfamily sequencing and Keep
Tool Needed Soonest are applied to minimize the number of component setups.
Classification of setup components into standard, semi-standard, and custom setup
components is performed to reduce the complexity of the component allocation
problem. A component allocation algorithm is developed to balance workload
across machines. Assigning board families to production lines is performed using a
modification of Longest Processing Time (LPT) rule. Assigning entire PCB
families to production lines to minimize makespan is difficult to accomplish since
the amount of production time for each family is very large compared to that of
individual PCB lot. Splitting some subfamilies is allowed as long as this does not
increase makespan. The PCB grouping, family decomposition, subfamily
sequencing, Keep Tool Needed Soonest (KTNS), and component setup
determination procedures are derived from published research results. The
component allocation and board assignment are developed in this research, as well
as an overall methodology to integrate the entire problem.
Data provided by published literature are employed to evaluate performance
of the component allocation algorithm and the integrated methodology. To examine
the applicability of the methodology, an industrial data is used with the total
imbalance due to setup time and placement time of individual PCB and global
makespan as the performance measures. Experimentation is conducted with
simulated data based on an industry data to investigate impact of threshold value,
feeder capacity, and characteristics of data sets on system performance. / Graduation date: 2002
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/32456 |
| Date | 20 September 2001 |
| Creators | Neammanee, Patcharaporn |
| Contributors | Randhawa, Sabah U. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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