An 8 bit microcontroller slave unit was designed, constructed, and tested to
demonstrate advantages and feasibility of master/slave parallel processing using
conventional processors and relatively slow inter-processor communications. An 8 bit
ISA bus controlled by an 80X86 is interfaced to a logic block that controls data flow to
and from the slave processors. The slave processors retrieve tasks sent by the master
processor and once completed, return results to the master that are buffered for the
master's retrieval. The task message sent to the slave processors has task description and
task parameters. The master has access to the bi-directional buffer and a status byte for
each slave processor. Considerable effort is made to allow the hardware and software
architecture to be expandable such that the general design could be used on different
master/slave targets. Attention is also given to cost effective solutions such that
development and possible market production can be considered. / Graduation date: 1999
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/33358 |
| Date | 13 January 1999 |
| Creators | Larsen, Steen K. |
| Contributors | Herzog, James |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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