With the success of the CounterDataFlow Pipeline microarchitecture developed by Oregon State University, there is increasing demand for a highly flexible high-level simulator modeling tool to support the further expansions and studies of the Counterflow pipeline processors family. This work examines the implementation of a Java-based execution-driven simulator modeling tool, bBlocks, which gains flexibility by identifying the independent parts in a micro system and partitioning them into reusable blocks. Two simulators have been constructed to demonstrate the possibility of bBlocks. / Graduation date: 2001
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/33422 |
| Date | 09 June 2000 |
| Creators | Chan, Chung-lun |
| Contributors | Lu, Shih-Lien |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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