An extremely important area that has enabled or will enable many of the
digital video services and applications such as VideoCD, DVD, DVC, HDTV, video
conferencing, and DSS is digital video compression. The great success of digital video
compression is mainly because of two factors. The state of the art in very large scale
integrated circuit (VLSI) and a considerable body of knowledge accumulated over
the last several decades in applying video compression algorithms such as discrete
cosine transform (DCT), motion estimation (ME), motion compensation (MC) and
entropy coding techniques. The MPEG (Moving Pictures Expert Group) standard
reflects the second factor. In this thesis, MPEG standards are discussed thoroughly
and interpreted, and a VLSI chip implementation (CMOS 0.35�� technology and 3
layer metal) of a variable length decoder (VLD) for MPEG applications is developed.
The VLD developed here achieves high performance by using a parallel and pipeline
architecture. Furthermore, MPEG bitstream patterns are carefully analyzed in order
to drastically improve VLD memory efficiency. Finally, a special clock scheme is
applied to reduce the chip's power consumption. / Graduation date: 1998
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/33741 |
| Date | 14 January 1997 |
| Creators | Zhang, Haowei |
| Contributors | Magana, Mario E. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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