A new structure for the implementation of bit/serial adaptive IIR filter is
presented. The bit level system consists of gated full adders for the arithmetic
unit and data latches for the data path. This approach allows recursive
operation of the IIR filter to be implemented without any global
interconnections, minimal delay time, chip area and I/O pins. The
coefficients of the filter can be updated serially in real time for time invariant
and adaptive filtering. A fourth order bit/serial IIR filter is implemented on a
2 micron CMOS technology clocked at 55 MHz. / Graduation date: 1992
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/36521 |
| Date | 29 January 1992 |
| Creators | Badyal, Rajeev |
| Contributors | Kiaei, Sayfe |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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