The motivation of this research is to study different cache designs for on-chip
caches that improve processor performance and at the same time
minimize the degradation to system performance caused by an increase in
the processor memory traffic. As VLSI technology advances we can have
bigger and more complex on-chip caches that could not have been possible
a few years ago. Results derived from on-chip caches and performance
issues are basically similar to off-chip caches. In this study, we will
concentrate on single level on-chip caches though there are many
interesting issues relating system performance, memory traffic and
multi-level caches. / Graduation date: 1992
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/36922 |
| Date | 16 April 1992 |
| Creators | Ho, Yui Luen, Ho, Jeremy Yui Luen |
| Contributors | Rathja, Roy C. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
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