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Layout Implementation of A 10-Bit 1.2 GS/s Digital-to-Analog Converter In 90nm CMOS

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Identiferoai:union.ndltd.org:OhioLink/oai:etd.ohiolink.edu:wright1515626468169571
Date January 2017
CreatorsChunchu, Vinay Kumar
PublisherWright State University / OhioLINK
Source SetsOhiolink ETDs
LanguageEnglish
Detected LanguageEnglish
Typetext
Sourcehttp://rave.ohiolink.edu/etdc/view?acc_num=wright1515626468169571
Rightsunrestricted, This thesis or dissertation is protected by copyright: all rights reserved. It may not be copied or redistributed beyond the terms of applicable copyright laws.

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