Advancement in cryptography over the past few decades has enabled a spectrum of security mechanisms and protocols for many applications. Despite the algorithmic security of classic cryptography, there are limitations in application and implementation of standard security methods in ultra-low energy and resource constrained
systems. In addition, implementations of standard cryptographic methods can be
prone to physical attacks that involve hardware level invasive or non-invasive attacks.
Physical unclonable functions (PUFs) provide a complimentary security paradigm for a number of application spaces where classic cryptography has shown to be inefficient or inadequate for the above reasons. PUFs rely on intrinsic device-dependent
physical variation at the microscopic scale. Physical variation results from imperfection
and random fluctuations during the manufacturing process which impact each device’s characteristics in a unique way. PUFs at the circuit level amplify and capture
variation in electrical characteristics to derive and establish a unique device-dependent
challenge-response mapping.
Prior to this work, PUF implementations were unsuitable for low power applications
and vulnerable to wide range of security attacks. This doctoral thesis presents a coherent framework to derive formal requirements to design architectures and protocols
for PUFs. To the best of our knowledge, this is the first comprehensive work that
introduces and integrates these pieces together. The contributions include an introduction
of structural requirements and metrics to classify and evaluate PUFs, design
of novel architectures to fulfill these requirements, implementation and evaluation of
the proposed architectures, and integration into real-world security protocols.
First, I formally define and derive a new set of fundamental requirements and
properties for PUFs. This work is the first attempt to provide structural requirements
and guideline for design of PUF architectures. Moreover, a suite of statistical properties of PUF responses and metrics are introduced to evaluate PUFs.
Second, using the proposed requirements, new and efficient PUF architectures are
designed and implemented on both analog and digital platforms. In this work, the
most power efficient and smallest PUF known to date is designed and implemented on ASICs that exploits analog variation in sub-threshold leakage currents of MOS
devices. On the digital platform, the first successful implementation of Arbiter-PUF on FPGA was accomplished in this work after years of unsuccessful attempts by the research community. I introduced a programmable delay tuning mechanism with pico-second resolution which serves as a key component in implementation of the
Arbiter-PUF on FPGA. Full performance analysis and comparison is carried out through comprehensive device simulations as well as measurements performed on a
population of FPGA devices.
Finally, I present the design of low-overhead and secure protocols using PUFs for integration in lightweight identification and authentication applications. The new protocols are designed with elegant simplicity to avoid the use of heavy hash operations
or any error correction. The first protocol uses a time bound on the authentication process while second uses a pattern-matching index-based method to thwart reverseengineering
and machine learning attacks. Using machine learning methods during
the commissioning phase, a compact representation of PUF is derived and stored in a database for authentication.
| Identifer | oai:union.ndltd.org:RICE/oai:scholarship.rice.edu:1911/71995 |
| Date | 16 September 2013 |
| Creators | Majzoobi, Mehrdad |
| Contributors | Koushanfar, Farinaz |
| Source Sets | Rice University |
| Language | English |
| Detected Language | English |
| Type | thesis, text |
| Format | application/pdf |
Page generated in 0.0023 seconds