Many wireline communication systems are moving toward a digital based architecture for the receiver that requires a front-end high-speed ADC. This thesis proposes a two-level time-interleaving topology for realizing such an ADC, comprising front-end time-interleaved sub-rate track-and-holds each followed by a sub-ADC which is further time-interleaved to a slower clock frequency. The design, implementation and measurement of the 1.25GS/s sub-ADC fabricated in 65nm CMOS technology is presented. The SAR architecture is chosen for its low power and digital friendly nature along with an unconventional C-2C capacitive DAC implementation for higher bandwidth. The time-interleaved C-2C SAR ADC runs with a 1.0V supply, and it has a full input range of 1.0V\subscript{pp} differential, while consuming 34mW. The SNDR is 39.4dB at low frequency and the FOM is 360fJ/conv-step and 428fJ/conv-step at low and Nyquist input frequencies respectively. The SNDR is 34dB at 4GHz input frequency, which is more than 6 times the Nyquist frequency.
| Identifer | oai:union.ndltd.org:TORONTO/oai:tspace.library.utoronto.ca:1807/43329 |
| Date | 11 December 2013 |
| Creators | Wang, Qiwei |
| Contributors | Chan Carusone, Anthony |
| Source Sets | University of Toronto |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
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