碩士 / 國立交通大學 / 資訊工程系所 / 93 / Low-power circuit design is the fashion of the future design guideline, especially not losing the speed performance. So far some research on stack is performed. However, their power performances are not good enough. The purpose of this paper is to present a power-efficient stack with clock-less design technique and its implementation. Based on GasP asynchronous control family from Sun Microsystems laboratories, we reduced the data movements in stack with the concept of master-slave temporal storages and n-place linear storages to low down the power consumption. For the ease of comparing with other targets in experiment, we implemented our stack with the same number of storages as the target’s one. Results from HSPICE simulations with UMC 0.18 model file show that our stack saved averagely 17% in power consumption with 100 random command sequences that are sized 100 compared to the re-implementation of original design in [1]. More than that, we gained averagely 91.39% in power consumption compared to linear stack. The cycle time is independent of the number of data items in the stack and the data width. It has constant time property. The energy consumption per stack operation depends on the sequence of stack operations.
| Identifer | oai:union.ndltd.org:TW/093NCTU5392044 |
| Date | January 2005 |
| Creators | 沈銘峰 |
| Contributors | 陳昌居 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | en_US |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 64 |
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