碩士 / 國立交通大學 / 電機學院碩士在職專班電信組 / 97 / When implementing a software-GPS-receiver (SGR), few bits analog-to-digital converter (ADC) are usually selected to reduce the required computation and storage. In this thesis, the performance degradation induced by few bits ADC is discussed and an improved structure called post-correlator phase compensation (PCPC) is proposed. The significant feature of the PCPC structure is the improvement of correlator output magnitude because it prevents the quantization effect on carrier phase ambiguity. The improvement becomes more critical when one-bit ADC is used.
On the other hand, in a SGR, the carrier synchronization typically adopts arctangent or its approximations as the phase discriminator because it maximizes SNR for analog signal cases. However, for few-bits ADC, this method greatly reduces the accuracy of phase estimate because of the significant quantization error. In this thesis, a novel phase discriminator, called NB-DPD, is proposed for one-bit ADC SGR. The statistical properties of the NB-DPD estimator are provided. The analytical results are verified by computer simulation. In addition, the NB-DPD is equivalent to DPD[1] in noiseless case and thus inherits high accuracy properties of DPD in high SNR cases. The NB-DPD performs generally better than the DPD in noisy cases. The lower the SNR is, the greater the improvement. Moreover, the NB-DPD works almost as well as arctangent-phase discriminator (APD) in low SNR environments and thus can be applied to GNSS receivers.
Finally, the NB-DPD is implemented in a one-bit software-defined GPS receiver using PCPC structure. The experimental results demonstrate the feasibility of the proposed scheme.
| Identifer | oai:union.ndltd.org:TW/097NCTU5435073 |
| Date | January 2009 |
| Creators | Yang, Ru-Muh, 楊儒木 |
| Contributors | Su, Yu T., 蘇育德 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | en_US |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 65 |
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