碩士 / 國立中央大學 / 電機工程研究所碩士在職專班 / 97 / IC product development procedure is more and more difficult with the rapid advance in manufacturing process. Current technologies can even allow analog and digital circuits in the same chip, which are called mixed-signal circuits. In order to deal with the circuit design complexity, computer-aided design tools are required to shorten the IC design process. Nowadays, these automated layout tools are fairly well developed and commercially available to digital designs. But the automated layout tools for analog circuits are still in their infancy. Analog circuit layout must consider many special constraints, such as symmetrical requirements, device matching, current density, parasitic effect, etc.. However, it is difficult to accurately estimate the parasitic effects and fix them before the layout is completed. Therefore, the layout design is more difficult in analog designs than in digital designs. In this thesis, an automation flow of OP Amplifier layout is proposed. Three common OP Amplifiers, folded cascade、current mirror and telescopic, are supported in this flow. It has been implemented using C++ program and Laker. All the generated layout can pass DRC and LVS verification.
| Identifer | oai:union.ndltd.org:TW/097NCU05441006 |
| Date | January 2009 |
| Creators | Feng-Yi Huang, 黃鳳儀 |
| Contributors | Chien-Nan Jimmy Liu, 劉建男 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 71 |
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