碩士 / 國立成功大學 / 工業與資訊管理學系專班 / 100 / The process of wafer level chip scale package (WLCSP) has advantages of high efficiency, high power and high density and it ensures consistent printed circuit board assembly necessary to achieve high yield and reliability. Due to the tendency of electronic appliances is with the light, thin, short, and small portable trend, WLCSP becomes the focus of future development. Though the package technology enhances electronic signal input/output density, low yield often appears in the early stage of introduction. Quite a few manufacturing factors influence the package process, and the height of solder ball on multilayer metallic film is the decisive one. Due to the sparse samples of pilot run in the early stage of new product development, the information that statistical process control charts provide is limited. This study is on the basis of timeline division and proposes the diffusion wavelet neural network which uses correlated virtual sample generating method proposed by Li et al. (2011) to improve the predictive performance of wavelet neural network for short-term time series. The diffusion wavelet neural network could more effectively improve the predictive accuracy than that of back-propagation neural network and grey-based forecasting method.
| Identifer | oai:union.ndltd.org:TW/100NCKU5041066 |
| Date | January 2012 |
| Creators | Hung-TaShin, 施宏達 |
| Contributors | Der-Chiang Li, 利德江 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 55 |
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