碩士 / 國立交通大學 / 電信工程研究所 / 103 / The technology of semiconductor device has developed fast for decades. In pursue to high performance and high packing density, the new process technology, the new devices'
structures, and even the new materials play the significant roles on the complementary metal-oxide-semiconductor (CMOS) technology scaling. Nowadays, the technology node
has been 16 nm. The planar MOSFET cannot provide good performance and is replaced by the multi-gate field effect transistors. Among the numerous types of multi-gate field
effect transistors, the FinFET device conforms to the demands of the costs for company and the manufacturing feasibility. However, the challenges for downscaling technology node to nanoscale become more severe. Besides the limitation on lithography, the characteristic
intrinsic fluctuation of devices is a restriction on device scaling. Exploring on the characteristics fluctuation of sub-16 nm FinFET devices has been an urgent priority. In this thesis, we discuss on the intrinsic fluctuation of sub-16 nm high-k/metal gate (HKMG)trapezoidal bulk FinFETs by using the experimentally calibrated 3D device and circuit
simulation. The explored fluctuation issues include random dopant fluctuation (RDF),line edge roughness (LER) and process variation effect (PVE). In the analysis on RDF,
we consider the two conditions of the trapezoidal FinFETs: the same top-fin width and the constant channel volume. In addition, the estimation on the power consumption from
the circuit operation of trapezoidal bulk FinFETs is included.
Our simulation results indicate that the influence of each type of LER on trapezoidal bulk FinFETs has weak dependence on the fin angle and the resist-LER/sidewall LER has large impact on the threshold voltage (Vth). Moreover, the modified fin patterning technology inducing LER, spacer-LER, has the least influence on the DC characteristics.
For the circuit operation, nearly-ideal bulk FinFETs have better performance on delay time, however, the fluctuation is larger due to the large gate capacitance variation.
Among those types of LER, the influence of resist-LER is most serious for characteristic fluctuation.
For RDF on the trapezoidal bulk FinFETs with different fin angles, the Vth fluctuation is getting larger as the fin angle is getting smaller under the condition of the constant
top-fin width, while the Vth fluctuation almost remains the same for each fin angle under the condition of the constant channel volume. It could provide an engineering thought
on the FinFET's structure design with respect to the process limitation on fabricating the rectangle-shape FinFET.
| Identifer | oai:union.ndltd.org:TW/103NCTU5435045 |
| Date | January 2014 |
| Creators | Huang, Wen-Tsung, 黃文聰 |
| Contributors | Li, Yiming, 李義明 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 119 |
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