碩士 / 國立聯合大學 / 電子工程學系碩士班 / 103 / This study describes the fabrication of a trench junctionless field-effect transistor (trench JL-FET) and asymmetric gate trench junctionless field-effect transistor (AG trench JL-FET). This study uses the dry oxidation to form the ultra-thin channel instead of directly depositing the thin-film as the poly-Si channel in JL-FET and it could get larger grain size and less grain boundary than directly depositing the thin-film. The dry etching process is utilized firstly in the fabrication of trench JL-FET is used to form a trench and define the channel thickness (TCH) and the gate length (LG) simultaneously. The trench structure was successfully and easily integrated into the JL-FET device.
The sub-threshold swing (SS) is 89mV/decade, and the ION/IOFF current ratio up to 106 due to the excellent gate controllability and ultra-thin channel. The trench JL-FET have a low drain induced barrier lowering (DIBL~0mV/V), indicating greater suppression of the short channel effect than in asymmetric gate JL-FET.
Firstly, this work focuses on the device process and basic device characteristics analysis. Next, the reliability analysis of trench JL-FET include high temperature performance, breakdown mechanism and hot carrier stress are investigated in this the analysis.
| Identifer | oai:union.ndltd.org:TW/103NUUM0428013 |
| Date | January 2015 |
| Creators | CHEN PING HUA, 陳秉樺 |
| Contributors | Yu-Hsien Lin, 林育賢 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 43 |
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