碩士 / 高苑科技大學 / 機械與自動化工程研究所 / 104 / In the semiconductor manufacture, the purpose of IC packaging, one of the back end processes, is to build the complete frameworks of IC chips while to protect the chips from physical damage and chemical change caused by the surroundings which will affect IC’s efficiency. For electronic signal distribution, on the other hand, an IC chip has to be connected with substrate or lead frames to form circuits and transmit signal between the chip and the carrier. Currently, wire bonding is the best approach of electrical interconnection.
In this research we use PLASKON_SMT-B-1LV to analyze one pair, two pairs and four pairs IC molding process. CAE simulation analysis of small size IC packaging has been developed for years. However, to predict the flow behavior of IC packages is still a huge challenge due to its geometric limitations. In this paper, one pair, two pairs and four pairs molding are studied for the investigation of the flow balance in different geometries with various GATE designs by using a CAE simulation software, Moldex3D R10. Furthermore, an optimized geometric design can be gained through the assistance of simulation and its results.
| Identifer | oai:union.ndltd.org:TW/104KYIT0689013 |
| Date | January 2016 |
| Creators | LIN,SIAN-CHANG, 林憲昌 |
| Contributors | Zhang Xu-Ming, 張旭銘 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 84 |
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