碩士 / 明新科技大學 / 電子工程系碩士班 / 104 / Emphasizing the high performance, high density, and low cost of IC products, the conventional IC products made with 2D structure can’t be satisfied. In the nano-node process, the fin field-effect transistor (FinFET) proposes the benefit to conquer this bottleneck and moves the advanced ICs to the deep nano-node generation, such as tsmc announced the process production with 10 nm process technology in 2017. Due to the FinFET with 3D structure, the gate control is better than the 2D traditional profile. The OFF current can be reduced more with FinFET structures.
In this experiment, the tested devices were fabricated with lithography following the over-exposure and dry etch technology as well as a set of 90 nm masks and the assistant of hard mask. The tested devices of p-type FinFETs with a fixed channel width (W = 0.11 μm) and the channel lengths (L = 0.1 μm, 0.5 μm, 2.0 μm) were chosen. Furthermore, the single-channel or multi-channel devices were also concerned with different VT energy implants (20 KeV and 15 KeV) and temperature stress (25°C, 50°C, 75°C, 100°C, 125°C) to probe the Early voltage (VA) whether these factors should be correlated more. The electrical characteristics of these tested devices with process split as well as VA value will be discussed.
According to the extracted data, the impact of Early effect at the short-channel device is not obvious under the single-channel or the multi-channel. In the whole consideration, the VA variation is not tremendous at the short-channel device. As the channel length with the temperature increase is increased, the VA change is not distinct. Considering the VT energy implants, the VA change under the lower VT energy implant is obvious as the temperature is increased due to the VT value easily transferred. However, the higher energy implant is not obvious. Through this study, the VA value related to the high, medium, and low electrical fields in channel also can be exposed. Providing a suitable and reasonable device model to IC designers is necessary. By the way, the difference of VA values and trends between hole carrier and electron carrier in FinFET channel under device size, stress temperature, and VT energy implants is tried to be explained.
| Identifer | oai:union.ndltd.org:TW/104MHIT0686007 |
| Date | January 2016 |
| Creators | TIEN,JHEN-WEI, 田振威 |
| Contributors | WANG,MU-CHUN, 王木俊 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 113 |
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