碩士 / 國立清華大學 / 電子工程研究所 / 104 / With the explosive growth of the demand for portable electronic products, internet of things, and cloud applications, the development of semiconductor memories has been the focus of much attention in these years. CMOS compatible embedded non-volatile memories have been widely introduced due to the high integration with integrated circuits. One-Time Programmable (OTP) memories with the benefits of low power and high reliability have been widely applied in parameter storage and circuit trimming.
A new operation scheme is proposed for achieving multi-level storage in FinFET OTP cells by high-κ metal gate (HKMG) CMOS process. This OTP cells programmed by breaking down of the gate dielectric layer, during which the corner effect in the FinFET structure shortens the program time and lowers program voltages. The after breakdown resistance in the storage node is found to be well controlled by the compliance current level set by the select transistor. Through the select gate voltage control, the multi-level OTP cell has been demonstrated for in advanced logic non-volatile memory (NVM) applications. Compare with the conventional OTP cell, MLC OTP allows the storage of two bits per cell. With only a slight increase in read voltage, the storage capacity of single cell is doubled. In addition, the superior data retention and disturbs immunity are verified by a long-term continuous read and baking under a high temperature. With these excellent properties, this new MLC OTP cells can be readily applied to conventional 2-level OTP memories for higher density applications.
| Identifer | oai:union.ndltd.org:TW/104NTHU5428045 |
| Date | January 2016 |
| Creators | Chen, Yu Zheng, 陳裕禎 |
| Contributors | Lin, Chrong Jung, 林崇榮 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 63 |
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