碩士 / 國立清華大學 / 工程與系統科學系 / 104 / For germanium (Ge) material, it provides two times electron mobility and four times hole mobility than silicon (Si). Therefore, Ge is used as channel material in SOI FinFET to obtain high channel mobility. The interface between Ge and high-k dielectric is also investigated to obtain ultra-thin equivalent oxide thickness (EOT) and reduced gate leakage current.
Ultrahigh vacuum chemical molecular epitaxy (UHV-CME) and ASM (EPSILON 2000+), two facilities in National Nano Device Laboratories (NDL), are used to form SiGe and SiGe superlattice layers. Hafnium dioxide (HfO2) is deposited by Atomic Layer Deposition (ALD) as gate dielectric.
In the first part, Si/SiGe multi-layer is epitaxially grown layer-by-layer in Si bulk FinFET. For SiGe+cap, the electrical characteristics are better than SiGe, because SiGe+cap has Si cap to suppress Ge diffusion; The electrical characteristics of SiGe super lattice such as Ion/Ioff ratio, drain current, Gm, carrier mobility and subthreshold swing are improved. We predict that Si is added to SiGe layers can achieve higher strain effect and lower Ge up-diffusion.
In the second part, Si/SiGe multi-layer is successfully epitaxially grown on Si fin channel in SOI FinFET by using UHV-CME. Si/SiGe super lattice is helpful to obtain better electrical characteristics compared to SiGe+cap layer and control sample, such as drain current, Gm, carrier mobility and subthreshold swing are improved. We predict that Si is added to SiGe layers can achieve higher strain effect and improve interface. Furthermore, Si/SiGe super lattice achieve higher Tinv 2.05 nm. Because of the thinner Si cap, it is difficult to improve Tinv.
In the third part, in order to remove oxide on Si wafer, we use pre-baking 900℃ before SiGe+cap epitaxially grown on Si fin channel in SOI FinFET by using UHV-CME. For without pre-baking 900℃, the characteristics of subthreshold swing and Gm are better than pre-baking 900℃. From TEM, we consider that high temperature suffer from poor interfacial quality; In addition, the thickness of Si/SiGe super lattice is modulated in the third part. The electrical characteristics of SOI FinFETs with different Si/SiGe super lattice are discussed. For the thick Si/SiGe super lattice, the electrical characteristics are better than thinner Si/SiGe one. Higher saturation drain current and mobility, and lower Tinv are achieved by thick Si/SiGe super lattice. In addition, good reliability can be achieved as well. We predict that thick Si cap can suppress Ge diffusion and thick Ge layers have more carriers in the channel.
| Identifer | oai:union.ndltd.org:TW/104NTHU5593018 |
| Date | January 2016 |
| Creators | Kao, Chia Hung, 高嘉宏 |
| Contributors | Chang-Liao, Kuei Shu, 張廖貴術 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 104 |
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