碩士 / 國立清華大學 / 工程與系統科學系 / 104 / A lattice mismatch exists between silicon and germanium material ,which induces a strain in Si/Ge channel FinFET. If a Ge epitaxy layer is under its critical thickness, a strain would be generated to promote carrier mobility. Epitaxy Si/Ge super-lattice is applied for SOI FinFET device in this thesis. Effects of Ge ratios in Si/Ge channel and are studied with different Si/Ge layer thicknesses as during epitaxy process.Higher carrier mobility in FinFET may be achieved by Si/Ge super lattice channel. A low-temperature microwave annealing is applied to achieve good activation after ion implantation, and its temperature can be around 400 ~500 oC . Compared to rapid thermal annealing , short channel effect induced by dopant diffusion can be suppressed by a microwave annealing for thermal activation . Also, the increases in equivalent oxide thickness of high-k dielectric layer after high temperature process may be minimized.
In the first part, Si/Ge multi-layers are epitaxially grown layer-by-layer on SOI substrate. FinFET with Si/Ge super lattice channel is successfully fabricated in this thesis. Experimental results show that electrical characteristics of device with Si/Ge super lattice are better as compared to those of control sample, such as higher drain current, transconductance , Ion/Ioff ratio and carrier mobility .The improvement can be attributed to the strained Si/Ge super lattice and suppressed Ge diffusion by Si cap. Moreover , electrical characteristics of device with Si/Ge super lattice channel formed by 2 Periods Si/Ge=25Å/25Å are the best among all samples, such as drain current, Ion/Ioff ratio, transconductance, mobility. Thus, Si cap on Si/Ge super lattice channel can achieve higher strain effect and lower Ge up-diffusion.
In the second part, FinFET with Si/Ge super lattice is used according to the results of the 1st part. In order to continuously promote electrical characteristics of FinFET, low-temperature microwave and rapid-thermal annealing treatments for dopant activation are investigated. Experimental results show that Tinv of 1.6nm and low gate leakage are achieved by a microwave annealing. Also, the off current of FinFET is reduced because the leakage current is suppressed by reducing dopants diffusion during activation process .However, the drain on current of device with a microwave annealing is smaller as compared to that with rapid thermal annealing.
| Identifer | oai:union.ndltd.org:TW/104NTHU5593042 |
| Date | January 2016 |
| Creators | Chen,Po Yen, 陳柏硯 |
| Contributors | Chang-Liao,Kuei-Shu, 張廖貴術 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 70 |
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