碩士 / 國立臺灣師範大學 / 光電科技研究所 / 104 / This is experimental demonstration integrating Ge FETs with ferroelectric HfZrOx gate stack for subthreshold swing (SS) < 60mV/dec and hysteresis-free by negative capacitance (NC) effect. The capacitance of semiconductor and ferroelectricity is matched to obtain the no VT shift for forward and reverse sweeps with hysteresis-free. The body factor and modeling are performed to validate the NC effect and optimize the Ge thickness by numerical calculation, respectively.
The FinFET with the fin width less than 50nm is as well know. The fin width of this work is ~60-80nm, therefore, we denoted our FET as fin-shaped FET. The small body volume of Fin-shaped is beneficial for well-control by gate to obtain steep threshold slope.The third chapter of this thesis introduces two types of fin width formation by conventional I-line stepper. The goal of this work is the narrow fin width to be achieved by NDL standard 6” process line.
The conventional process of TFET have to individual mask for source and/or drain with different ion implant (I/I) species, this may lead the space between gate to source/drain, which may lead lower BTBT. In this work, the narrow fin process using all I-line photolithograph stepper without e-beam writer is proposed. The self-aligned I/I process for source/drain and no space between gate to source/drain will be demonstrated.
Keyword: steep subthreshold swing, fin-shaped FET, fin-shaped TFET.
| Identifer | oai:union.ndltd.org:TW/104NTNU5614008 |
| Date | January 2016 |
| Creators | Liu, Shau-Nung, 劉劭農 |
| Contributors | Lee, Min-Hung, 李敏鴻 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 78 |
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