碩士 / 國立臺灣大學 / 光電工程學研究所 / 104 / After describing Moore’s Law, we introduce node technology progression of semiconductor manufacturing in this thesis, including the corresponding challenges and the solution to them. After studying research trends, we predict sub-10nm node technology development, and introduce short-channel effects (SCEs) and narrow-channel effects (NCEs) briefly.
In the first part, we introduce III-V material characteristics, and their developing history and operating principles of high electron mobility transistors (HEMTs). We propose fin structures of HEMTs, and use TCAD to simulate. From simulation results, the theory of gate control mechanisms is proposed. We fabricate and measure the device, the measurement results can be explained by the proposed theory successfully.
In the second part, we introduce ferroelectric material to form negative capacitance (NC), and use two different viewpoints of circuit and energy to explain it. We fabricate MOS capacitances and discuss their C-V, I-V, and interface characteristics at different crystalline temperatures and frequencies.
In the third part, we introduce development, pros and cons of negative capacitance field effect transistors (NCFETs). We fabricate and discuss their I-V characteristics in different crystalline temperatures. Finally, we use TCAD to simulate different conditions of NCHEMTs, and the results are regarded as improving ways in the future.
| Identifer | oai:union.ndltd.org:TW/104NTU05124137 |
| Date | January 2016 |
| Creators | Chia-Ming Chang, 張家銘 |
| Contributors | Chao-Hsin Wu, 吳肇欣 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 95 |
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