碩士 / 國立高雄大學 / 電機工程學系碩士班 / 104 / Semiconductor devices have been continually improved to become lighter, thinner, shorter and smaller. In this field, the 3D-structure FinFET is considered as a technical breakthrough and stated by some researches as the possible devices to replace the traditional 2D-structure transistors. This thesis was centered on the basic electric measurement and reliability when the FinFET of MultipleFin undergoes the Positive Bias Temperature Instability.
In case of N-Type, in this study, we found the electric property of thin FinFET in Metal Gate TaN layer performs better than the counterpart in thicker layer of Metal Gate TaN. Then the researchers applied both thinner and thicker layers of Metal Gate TaN to positive bias temperature instability (PBTI) test.
Upon applying time power law exponent, researchers obtained a value “n” which indicates the thicker and thinner layers of Metal Gate TaN would be tended to oxide defects when under different gate voltages and the “n” value was approximately “0.2”.
The thicker layer of Metal Gate TaN could undertake more influence from gate voltages. For the thicker layer of Metal Gate TaN, the researchers suggested that gate voltages would be less able to influence device channel. However, the level of degeneration of elements would become more serious when the layer affected by PBTI. As a result, the thinner layer of Metal Gate TaN could provide higher element reliability.
| Identifer | oai:union.ndltd.org:TW/104NUK05442004 |
| Date | January 2016 |
| Creators | PING-HAN CHUNG, 鍾秉翰 |
| Contributors | Wen-Kuan Yeh, 葉文冠 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 74 |
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