碩士 / 國立中興大學 / 電機工程學系所 / 105 / As devices scale down, VDD is scaled consistently due to power reduction. The subthreshold swing (S.S.) with 2.3KbT/decade for MOSFET in room temperature restricts the switch characteristics. To overcome such limits, a lot of researchers proposed to improve such a situation by connecting metal-insulator-metal (MIM) negative capacitance with ferroelectric materials (FE) as the dielectric layer in series and stacking on the gate. Such an advantage not only could reduce the power dissipation in steady state but also could be rapidly turned on under low voltage.
TCAD simulation is applied to study the device characteristics of NC-FET in this study. HZO is used for the FE layer, and the structure is 3D SOI FinFET. In this study, analytic functions are established for directly fitting the voltage gain experimental data of NC-FET. The data from two different annealing temperatures are utilized, with interpolation and extrapolation, for predicting the voltage gain from other annealing temperatures. The gate voltage with/without taking the NC effect into account is put in the TCAD simulator to simulate the ID-VG characteristics. The proposed approach could predict the ID-VG characteristics of NC-FinFET under different annealing temperatures and could be expanded to transistors with other structures, such as Bulk FinFET or Nanowire transistor, and distinct ferroelectric materials. Such an analytical model could also be established on the SPICE circuit simulation in the future to simulate the characteristics of NC-FET being applied to circuit design.
Key word：NC、SOI FinFET、FE、S.S.、Nanowire transistors
| Identifer | oai:union.ndltd.org:TW/105NCHU5441014 |
| Date | January 2016 |
| Creators | Kung-Hsien Lin, 林恭賢 |
| Contributors | Shu-Tong Chang, Ming Tang, 張書通, 湯銘 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 64 |
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