碩士 / 國立中興大學 / 電機工程學系所 / 105 / In order to overcome the physical limitation of the device scaling, the ferroelectric (FE) with a negative capacitance effect can be applied to solve this kind of problem, so that Subthreshold Swing (SS) can be lower to 60 mV / dec and the effect of device quick opening can be realized in the low voltage condition. In this thesis, the device characteristics of negative capacitance transistors were studied by TCAD simulation. The adoptive ferroelectric with a negative capacitance effect was HfZrO2, and it was applied to the Silicon-On-Insulator FinFET and planer MOSFET respectively to compare the performance differences of the devices. Then based on the experimental result from the HZO under the two annealing temperature conditions, and mathematical model was applied to forecast the device characteristic changes of SOI FinFET and planer MOSFET with ferroelectric material in different annealing temperatures. According to the simulation results, the negative capacitance effect of HZO was more obvious under a high annealing temperature. It is shown in the research results that the HZO has a better negative capacitance effect when applied to SOI FinFET than to planer MOSFET. In addition, the mathematical model in this thesis not only can be utilized to forecast current-voltage characteristic of SOI FinFET and planer MOSFET with negative capacitance effect under the different annealing temperatures, but also can be used to the transistor with other structures, such as the bulk FinFET, nanowire transistor and other ferroelectric materials.
| Identifer | oai:union.ndltd.org:TW/105NCHU5441023 |
| Date | January 2016 |
| Creators | Yi-Lu Dai, 戴易錄 |
| Contributors | Shu-Tong Chang, 張書通 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 66 |
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