碩士 / 國立中央大學 / 電機工程學系 / 105 / Following the rapid development of integrated circuit technology, the quest for integrating high-mobility channel metal-oxide-semiconductor field-effect transistors (MOSFETs) has become even more urgent because current aggressively scaled devices are approaching their physical limit. As indicated by the recent status of material technology, Ge, which has higher hole mobility than Si, is likely to be the choice for p-channel MOSFETs, while high electron mobility III-V materials, such as InGaAs, could be used for the n-channel MOSFETs. However, to realize the integrated Ge and InGaAs CMOS scheme, one has to cope with the complex structure and composition of the native oxides of Ge and InGaAs, which result in defect states at the oxide-semiconductor interface. Since the gate-stack process of Ge MOS, which involves rapid thermal oxidation (RTO), is a rather mature process, this work is devoted to the development of a common gate-stack process based on this process so that it can be used to fabricate Ge and InGaAs fin field effect transistors (FinFETs) simultaneously.
In this study, Al2O3 prepared by atomic layer deposition (ALD) is used as a high dielectric constant material. The feasibility of this common gate-stack process is evaluated based on the characteristics of Ge and InGaAs metal-oxide-semiconductor capacitors (MOSCAPs). The Ge and InGaAs epilayers were chemically cleaned in an HF solution and subjected to a RTO process. Then, the samples were treated by nitrogen plasma right before the deposition of the Al2O3 gate dielectric. Post metal annealing (PMA) was performed to reduce the oxide traps and the border traps near the oxide-semiconductor interface. The Ge and InGaAs MOSCAPs prepared by the nitrogen plasma treatment show effective capacitance modulations of 55% and 72%, respectively. Their interface trap density is 7.85×1011 eV-1cm-2 near the valence band, and 2.58×1011 eV-1cm-2 near the conduction band, respectively, as extracted by the conductance method. It indicates that nitrogen plasma treatment can effectively decrease interface traps in both InGaAs and Ge MOSCAPs. A series heating experiments shows that nitrogen plasma treatment can also improve the thermal stability of MOSCAPs. After rapid thermal annealing at 550°C, the dispersion of CV curves in accumulation region decreases from 3.4%/dec to 2.5%/dec for the InGaAs MOSCAP and from 1.47%/dec to 0.94%/dec for the Ge MOSCAP. In addition, the Ge MOSCAP’s modulation improves from 72% to 83%.
After confirming the common gate process parameters, the proposed gate-stack process was used to fabricate junctionless (Ge,InGaAs) FinFETs. The Ge channel layer material was grown on a silicon-on- insulator (SOI) substrate by low pressure chemical vapor deposition, and the InGaAs channel layer material was grown on an InP substrate with an InAlAs buffer layer by molecular beam epitaxy (MBE). The gate length (Lg) and fin width (Wfin) of the Ge pFinFET and InGaAs nFinFET prepared by electron beam exposure are 80 nm/30 nm and 40 nm/60 nm, respectively. The Ge and InGaAs FinFETs exhibit Ion/Ioff ratio of 104 and 103, subthreshold swing of 180 mV/de and 384 mV/dec, and maximum drain current of 60 µA/µm and 2 µA/µm, respectively. The gate leakage current for both the Ge and InGaAs FinFETs is below 10-4 µA/µm. Although the drain current density of the InGaAs FinFETs is unexpectedly small, which may be due to over etching, this work has demonstrated the feasibility of this common gate process for Ge/InGaAs CMOS integrated circuits.
| Identifer | oai:union.ndltd.org:TW/105NCU05442075 |
| Date | January 2017 |
| Creators | Nai-Rong Hsu, 許乃蓉 |
| Contributors | Jen-Inn Chyi, 綦振瀛 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 88 |
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