碩士 / 國立高雄大學 / 電機工程學系碩博士班 / 105 / In past several decades, complementary metal-oxide-semicondutor (CMOS) technology has been development aggressively. In order to enhance device performance and suppress leakage for scaling device, high-k (HK) materials and metal gate (MG) electrodes have become an important foundation of CMOS technology processes. In recent years, HfO2 gate dielectric integrated with metal gate was used to replace Poly-Si /SiO2 gate structure. But there may exist defects in HfO2 gate dielectric, defects have caused serious trapping effect in p-type metal-oxide-semicondutor field-effect transistors (pMOSFETs), resulting in some electrically and reliability issues. By the way, excessive low-frequency noise will cause a limitation of the functionality for analog/ mixed-signal and RF circuits.
In this paper, Random Telegraph Noise (RTN) was used to analysis small dimension device. First, we choise the small dimension devices on the edge of wafer, because the devices on the edge of wafer easier happen Process-Induced Defects. We have investigated the trapping/de-trapping properties of interfacial layer trap interact with channel, and extracted some important parameters. After the accurate analysis on Random Telegraph Noise (RTN) in high-k dielectric devices, we determine an oxide trap is located in high-k layer and then investigate drain current flutuation.
Further, we choose devices on the center of wafer, and find fresh devices that without RTN current fluctuation. The study stress devices to induce defects by CVS, and this method is known as Stress-Induced Device’s Defects, and then investigate device performance and defect depth with different voltage by this method. In terms of device performance, high stress voltage transcondutance and drive current have severe degradation than low stress voltage, because Si-H bonds become weak and disconnecting and then produce dangling bonds. The dangling bonds interact with carriers, and result in device performance degradation. In terms of RTN, the trapping/de-trapping properties of interfacial layer trap interact with channel, and extracted some important parameters. We accurate calculate defects depth, and found that high stress voltage induced defect is close to high-k/IL-SiO2 interface than low stress voltage does, and then these defects are easier to interact with channel substrate to further degrade device performance.
| Identifer | oai:union.ndltd.org:TW/105NUK00442025 |
| Date | January 2017 |
| Creators | YANG, CHENG-KAI, 楊程凱 |
| Contributors | YEH, WEN-KUAN, 葉文冠 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 77 |
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