碩士 / 國立臺北科技大學 / 電子工程系研究所 / 105 / With reducing the gate length of MOSFETs in advanced process technology, the short channel effects would be problematic. In recent years, FinFETs were developed to enable control of the short channel effects. We study the FinFET technology for RF and power applications in this thesis. RF and power FinFETs were fabricated using a bulk-Si FinFET process. For RF applications, devices were designed with a multi-fin and multi-gate layout to reduce the gate resistance and increase the total drain current as well as transconductance. However, FinFETs exhibit higher parasitic capacitances due to their 3-D structures. Therefore, the speed of FinFETs is limited. To reduce the parasitic capacitances, we modified and designed the devices with different geometrical parameters. Besides, a novel device layout with a pectinate S/D contact area was proposed. Through the characterization of devices with different geometries, we found a guideline for device layout design.
For power applications, the DEMOS technology was adopted in our FinFET devices. Conventional drain-extended FinFETs have a trade-off between breakdown voltage and on- resistance. To solve this problem, we proposed two types of power FinFET structures. By analyzing the DC and high-frequency characteristics, including transconductance, breakdown voltage, cutoff frequency and maximum oscillation frequency, we found a design guideline for RF power FinFETs.
| Identifer | oai:union.ndltd.org:TW/105TIT05427050 |
| Creators | Ming-Lung Chen, 陳銘龍 |
| Contributors | Kun-Ming Chen, Hsin-Hui Hu, 陳坤明, 胡心卉 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 0 |
Page generated in 0.0127 seconds