碩士 / 明新科技大學 / 電子工程系碩士班 / 106 / The applications of FinFET device with advanced nano-node process are more and more adopted in the commercial electronic products, especially in high-performance and high-density products. In order to obtain the optimal electrical characteristics and controllable process window for the desired devices, the electrical parameters for devices must be strictly monitored and verified.
In this work, one set of 90nm lithographical masks with hard masks were applied to form the FinFET devices with the adjustment of exposure energy in lithography and the control of parameters of dry etch process. Using these fabricated FinFET devices, we probe the channel length reduction (ΔL) and the source/drain resistance (RSD) related to the source/drain extension lengths (LSDE).Besides correlating the published literatures, we hope this work can provide some niche benefiting the IC designers and process teams in the optimization of device density and controllable process window.
In this measurement experiment, there are two LSDE: 60 and 160nm. The tested devices with fixed channel length (W=0.11μm) were L=(0.12, 0.16, 0.24, 0.5, 2, 10)μm for p-type FinFETs and L=(0.12, 0.16, 0.24, 2, 10)μm for n-type FinFETs, respectively. The extracted consequences for p-type FinFETs show ΔL=5.51nm and RSD=44.1kΩ at LSDE=60nm and ΔL=126nm and RSD=102kΩ at LSDE=160nm. At the same time, the extracted for n-type FinFETs demonstrate ΔL=9.1nm and RSD=25.4kΩ at LSDE=60nm and ΔL=22.5nm and RSD=51.8kΩ at LSDE=160nm. Because the doping species and concentration for n-type or p-type FinFETs are different, the extracted results are also various.
| Identifer | oai:union.ndltd.org:TW/106MHIT0686009 |
| Date | January 2018 |
| Creators | CHANG,CHIA-HSIEN, 張家憲 |
| Contributors | XU,FU-GUO, 徐復國 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 65 |
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