碩士 / 國立交通大學 / 電子研究所 / 106 / In current semiconductor device process, the process variability is a crucial issue. For all characteristics associated with process variation, random variation of threshold voltage is especially important. In this thesis, with the help of commercial 3D technology computer-aided design (TCAD) Sentaurus, we build up our simulation structure calibrated with respect to Intel published 14-nm technology node FinFET device. TiN is chosen to be the metal gate material. We assume metal gate granularity (MGG) as the main source of process variation to simulate the distribution of threshold voltage variation. Meanwhile, we also discuss the effect of different average grain size (AGS). Furthermore, with the consideration of MGG, we add an oxide charged trap at the interface to induce random telegraph noise (RTN), and consequently cause threshold voltage shift (ΔVth). We find that with the device scaling, the correlation between maximum RTN ΔVth and process variation grows stronger. Besides, the impact of RTN becomes significant enough to compete with the process variation as device shrinks and AGS decreases. In addition, we perform simulations on ΔVth variation due to multiple traps induced by BTI stressing. We analyze the relation between it and trap density under conditions of different device scales and AGS. Through this statistical simulation work, we provide a reference for device designing.
| Identifer | oai:union.ndltd.org:TW/106NCTU5428062 |
| Date | January 2017 |
| Creators | Weng, Heng-Jui, 翁珩瑞 |
| Contributors | Chen, Ming-Jer, 陳明哲 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 41 |
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