碩士 / 國立交通大學 / 電子研究所 / 106 / This thesis proposes a new and simple hot-chuck measurement method for the extraction of the thermal resistance of FinFETs. The intrinsic transconductance that eliminates the parasitic source/drain resistance effect can serve as a temperature sensor to characterize the device temperature rise due to self-heating. Our method requires only DC measurements without the need of specific test patterns. In addition, based on 5-nm technology node, we have investigated the optimum stacking number for vertically stacked nanowire FETs. Our study indicates that the contact resistivity is crucial to the optimum stacking number. The vertical pitch of nanowires is also crucial to the optimum stacking number due to the parasitic capacitance. Our study indicates that air spacer may be the most efficient method to improve the logic performance of the nanowire FETs.
| Identifer | oai:union.ndltd.org:TW/106NCTU5428079 |
| Date | January 2017 |
| Creators | Huang, Wei-Cheng, 黃威程 |
| Contributors | Su, pin, 蘇彬 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 68 |
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