碩士 / 國立清華大學 / 電子工程研究所 / 106 / Since dimensions of device channel shrink, several Short Channel Effects (SCEs) appear. The FinFET which provides excellent gate control over short channel effects is considered one of the major solutions. However, the three-dimension device provides a lot of parasitic components which reduce the performance. The parasitic components of FinFET become one of the key limiting factors in achieving the target device performance beyond the 10 nm technology node.
The object of this thesis is to establish the effects of FinFET model on its parasitic capacitances, parasitic resistances, and RC time constant with 3D device simulations. The gate to spacer capacitance is the most dominant parasitic capacitance. It ramps up from a negligible weight of 19.8% to 25.5%. The Source/Drain contact resistance is the most dominant resistance. It ramps up from a negligible weight of 10.7% to 33.1%. Moreover, the RC time constant is an upward trend beyond the 10nm technology node. At last, by adjusting the fin height and the fin width, the parasitic capacitances and resistances with respect to fin geometry of FinFET are analyzed. In order to improve the performance of the device, the device geometry has to be optimized.
| Identifer | oai:union.ndltd.org:TW/106NTHU5428060 |
| Date | January 2018 |
| Creators | Wang, Han-Yang, 王翰揚 |
| Contributors | Lien, Chen-Hsin, 連振炘 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 72 |
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