碩士 / 國立臺灣師範大學 / 機電工程學系 / 106 / Traditional nonvolatile memory, such as SONOS Flash has disadvantages of high operating voltage, random dopant fluctuation, tunneling oxide induced leakage, random telegraph noise, and the other scaling limitation. These shortcomings make integration difficult, so, numerous efforts have been made on looking for future generation emerging memory.
On the other hand, Resistive Random Access Memory ( RRAM ) has an advantage of low power consumption, easy integration in the BEOL ( Back End of Line ) and logic circuit. Because of a simple stacked structure can be completed, or even zero mask integration possible, RRAM has a great potential for better embedded memory applications.
RRAM is divided into two categories according to operation type: unipolar RRAM and bipolar RRAM. Different mechanisms occur depending on the material of the upper and lower electrodes and the material of the dielectric layer. The bipolar RRAM is used in our work. In this paper, the composition of the RRAM used in this study consists of a TiN top electrode and a transition metal oxide layer, and a highly doped semiconductor source region of FinFET, with an underlap underneath the spacer.
In this work, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14nm-node HKMG FinFET CMOS platform. The result has shown that RRAM can have low operation voltage ( <3V ) and program within 100ns, also the demand for the maximum current is lower than 1mA. The reliability results have shown more than 400-time cycling for the endurance test and more than 1000-time window has been maintained for the retention test in the pFinFET RRAM. For the nFinFET RRAM, the reliability results have shown more than 1000-time cycling for the endurance test and more than 150-time window has been maintained for the retention test.
On the design of an RRAM memory array architecture, we used “active fin isolation” as a selector between two storage units. The transistor plays the role of switch, we put the switch and storage unit in series to replace the traditional crossbar architecture. In addition to using the transistor to limit the read and write current, sneak current can be suppressed efficiently. The simulation result shows that the new architecture can reduce a huge amount of power consumption and standby power. Especially, 30% and 99% reduction of the standby and active power have been also achieved, which shows the effective usage of the active-fin-isolation ( AFI ) in the FinFET RRAM array. Eventually, the disturbances of FinFET RRAM array during operation have also been investigated. The AFI and periphery RRAM close to the selected cell have been un-disturbed during the test. The selected control transistor has shown slightly increase of Vth shift, but this few increment will not hurt the driving capability for a control transistor to program the RRAM. These experimental and simulated results offer strong and solid results to elaborate the potential opportunities of the bipolar FinFET RRAM for embedded memories, especially for advanced CMOS technology node beyond 20nm.
| Identifer | oai:union.ndltd.org:TW/106NTNU5657002 |
| Date | January 2017 |
| Creators | Kuo, Yen-Chen, 郭彥成 |
| Contributors | Liu, Chuan-Hsi, 劉傳璽, 莊紹勳 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | zh-TW |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 57 |
Page generated in 0.0094 seconds