<p>The Fast Factorized Back Pro jection (FFBP) algorithm is a computationally efficient </p><p>algorithm for image formation in a Very High Frequency Synthetic Aperture Radar (VHF </p><p>SAR) system. In this report an investigation of the feasibility of using an FPGA with a </p><p>hard CPU core to calculate the FFBP in real-time has been done. Two System on a Chip </p><p>designs for this task have been proposed for calculating the FFBP. A simplified version of </p><p>the FFBP has also been implemented in Matlab and used during this pro ject. The result </p><p>is that the computationally intensive parts, such as index generating and interpolation </p><p>calculations, should be implemented in the logic part of the FPGA and the CPU should </p><p>handle scheduling. This kind of modular system is easy to maintain and upgrade.</p>
| Identifer | oai:union.ndltd.org:UPSALLA/oai:DiVA.org:hh-280 |
| Date | January 2006 |
| Creators | Hast, Andreas, Johansson, Lars |
| Publisher | Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), Högskolan i Halmstad/Sektionen för Informationsvetenskap, Data- och Elektroteknik (IDE) |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, text |
Page generated in 0.0024 seconds