In this report the two-tone PLL circuit intended for on-chip test of RF blocks is presented. The primary application is the third order intermodulation test (TOI), vital for RF front-ends. If the spectral analysis can also be completed by DSP available on the chip or on board, it provides a built in self-test (BiST) which can replace costly test instrumentation (ATE). The advantage of the designed two-tone PLL is that it practically prevents the locking effect while keeping the two oscillation frequencies close. Also by careful design the possible intermodulation distortion of the two-tone stimulus can be avoided. The two-tone PLL has been designed and verified at the system level using Verilog-A models in Cadence TM. Besides, two building blocks of the PLL were implemented at the circuit level in 90nm CMOS technology. The obtained results are promising in terms of a practical two-tone BiST implementation.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-18590 |
| Date | January 2009 |
| Creators | Shuaib, Muhammad |
| Publisher | Linköpings universitet, Institutionen för systemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/masterThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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