Creating an IC (Integrated Circuit) can be very time consuming if high flexibility of the construction is demanded. This report will try to solve this problem by creating own standard cell libraries, which in turn are more flexible since the user designs them. Having these libraries makes it possible to map VHDL or Verilog code to those libraries, using them instead of predefined cell libraries. The procedure of creating the libraries is quite time consuming, and thus the possibilities of making that procedure automatic, or as automatic as possible, has been examined. Unfortunately some manual labour has to be done, butthe process can be speeded up a lot by making parts of it automatic.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-2832 |
| Date | January 2005 |
| Creators | Jansson, Emil, Johansson, Torgny |
| Publisher | Linköpings universitet, Institutionen för systemteknik, Linköpings universitet, Institutionen för systemteknik, Institutionen för systemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
Page generated in 0.0072 seconds