In this thesis the new Speedster HP FPGA from Achronix is analyzed. It makes use of a new type of interconnection technology called picoPIPE™. By using this new technology, Achronix claims that the FPGA can run at clock frequencies up to 1.5 GHz. Furthermore, they claim that circuits designed for other FPGAs should work on the Speedster HP after some adjustments. The purpose of this thesis is to study this new FPGA and test the claims that Achronix make about it. This analysis is carried out in four steps. First an analysis of how the new interconnection technology works is given. Based on this analysis, a number of small test circuits are designed with the purpose of testing specific aspects of the new FPGA. To analyze circuit reusability an image filter designed by Synective Labs AB for a different FPGA architecture is adapted and evaluated on the Speedster HP. Lastly, an encryption circuit is designed from scratch. This is done in order to test what can be achieved on the Speedster HP when the designer is given full freedom.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-91792 |
| Date | January 2012 |
| Creators | Peters, Christoffer |
| Publisher | Linköpings universitet, Elektroniksystem, Linköpings universitet, Tekniska högskolan |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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