iii Abstract The goal to this research was to develop a scheme to optimize a digital filter design using an optimization engine and hardware-accelerated simulation using a Field Programmable Gate Array (FPGA). A parameterizable generic digital filter, which was fully implemented on a prototyping board with a Xilinx Virtex-II Pro xc2vp30-7-ff896 FPGA, was developed using Xilinx System Generator for DSP. The optimization engine, which actually is a random candidate generator that will eventually be replaced by a differential evolution engine, was implemented using MATLAB along with a candidate evaluator and other supporting programs. Automatic hardware co-simulations of 100 candidate filters were performed successfully to demonstrate that this approach is feasible, reliable and efficient for complex systems.
| Identifer | oai:union.ndltd.org:UTENN/oai:trace.tennessee.edu:utk_gradthes-1334 |
| Date | 01 May 2007 |
| Creators | Liang, Getao |
| Publisher | Trace: Tennessee Research and Creative Exchange |
| Source Sets | University of Tennessee Libraries |
| Detected Language | English |
| Type | text |
| Source | Masters Theses |
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