A versatile I/O system for a real time image processor and a complex clocking circuit for the I/O system and the image processor have been designed. The I/O system receives data from an arbitrary video source. These data are digitized and conditioned to be compatible with the image processor. The image processor output is conditioned such that these data can be displayed on a standard RS l7O 2:l video monitor. Variable frame rate reduction. circuits and. bit reduction techniques such as line, column and dot interlace are incorporated during output conditioning. Experiments on reducing the frame rate and bit rate of a processed image can be carried out using this I/O system. / Master of Science
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/45642 |
| Date | 14 November 2012 |
| Creators | Adkar, Sanjay |
| Contributors | Electrical Engineering, Nadler, Morton, Armstrong, James R., Tront, Joseph G. |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Thesis, Text |
| Format | viii, 192 leaves, BTD, application/pdf, application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | OCLC# 15183236, LD5655.V855_1986.A343.pdf |
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